Floating gate memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) or flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPPROMs may have source and drain regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Many types of EEPROMs and flash EEPROMs use merged select/control gate electrodes to reduce the size of the memory cell. By merged, it is meant that one or more conductive members or layers form both the select gate and control gate of the memory cell. If more than one conductive member or layer is used for the merged select/control gate, the members or layers are electrically connected together, so that they are at about the same potential. The select gate portion of a conductive member of a merged select/control gate is typically formed by a masking operation. A non-functional or poorly functioning memory cell is formed if the channel region between the source region and floating gate or between the drain region and the floating gate is not covered by the conductive member. As dimensions of memory cells become smaller, misalignment of masking layers becomes more important. A memory cell is typically sized larger if misalignment tolerances must be taken into account.